Recently. Socionext announced that it is expanding 3DIC technology into mass production, not only serving everyday consumer electronics but also meeting the rigorous demands of artificial intelligence (AI) and high-performance computing (HPC) in terms of computing power and energy efficiency. This advancement is like pressing fast-forward on the "urbanisation" of chips.

For decades, chip performance improvements primarily relied on process node shrinkage, making transistors smaller and packing them densely. But today, advanced nodes such as 3mm and 5nm are approaching physical limits. Further shrinking not only becomes prohibitively expensive but also makes yield maintenance extremely challenging. As a result, engineers are changing their mindset: if there's no more room to expand horizontally, why not stack chips like LEGO blocks? Different computing units, memory units, and interface modules no longer lie in a single plane-they are distributed across the "floors" of a skyscraper. In this way, die area is no longer the bottleneck, and new design possibilities emerge.

This time, Socionext introduces a fully packaged chip using ISMC's advanced stacking technology. A 3nm computing core and a 5nm I/O chip are tightly stacked face-to-face. While 2D designs can extend horizontally to accommodate more functions, they are ultimately constrained by "land." 3D stacking, on the other hand, is like building a skyscraper on the same footprint, instantly raising the performance ceiling.

Interestingly. Secionest doesn't stop at simple 3D stacking. Their 5.5D design is more like planning a "city cluster." Imagine a single chip substrate containing multiple vertical skyscrapers while also hosting several functional zones —logic, memory, and interface manufactured using the most suitable process nodes, interconnected through complex pathways. The result is a well-coordinated "city" where each zone performs its function efficiently while collaborating with others.

This represents the future direction of heterogeneous computing: integrating modules of different processes and functions, rather than endlessly pushing the limits of a single core.

Al and HPC are among the most voracious consumers of computing power today. Training a large model requires massive numbers of computing and memory units working efficiently together. Traditional chip designs are like hundreds of ordinary vehicles struggling to transport goods— speed and efficiency are inherently limited.

3DIC, however, is more like building a multi-layered expressway. The distance between computing and memory units shrinks dramatically, bandwidth rises, and latency drops. For Al, this means faster model training and inference; for HPC, it enables complex scientific simulations and data analysis in shorter timeframes. More importantly, 3D stacking is not just an experimental niche for cutting-edge computing. As mass production matures, it can gradually permeate consumer electronics, including smartphones, tablets, and smart home devices, like skyscrapers first appearing in financial districts but eventually spreading to more areas.

In the chip world, performance is never the only consideration. Power consumption and cost often determine whether a technology can truly scale. The core logic can be made using the most advanced 3nm node, while less demanding I/O modules can use mature 7nm or nm processes. In other words, 3D stacking isn't just "piling on performance"; it's a smarter allocation of resources. This flexibility is key to its adoption in mass production.

Socionext's latest move signals that the chip industry is entering a new stage. Historically, growth relied on Moore's Law-smaller transistors and higher performance. Today, relying solely on size reduction is no longer sustainable. 3DIC opens a new upward path for semiconductors. It shows that future chips will not just be smaller—they will be more three-dimensional; not just single-core powerhouses, but multi-module ecosystems.

While 3DIC may sound abstract or distant, its impact is closer to everyday life than it seems. In the coming years, you might experience smoother AI assistants in the next generation of smartphones, faster large-model training in data centres, and more precise simulations in scientific research.

（Writer：Lany）